(1) Field of the Invention
The present invention relates to a fixed-length cell multiplex transmission apparatus, a fixed-length cell multiplex transmission method, a fixed-length cell multiplex transmitting apparatus, a fixed-length cell multiplexing apparatus, and a fixed-length cell distributing apparatus; all of which are suitable for use in a system (e.g., an ATM network) which transfers information to be transferred by dividing it into units of fixed-length cells [ATM (Asynchronous Transfer Mode) cells].
(2) Description of the Related Art
FIG. 39 is a block diagram showing one example of a general fixed-length cell (ATM cell) multiplexing/distributing processing system. As shown in FIG. 39, a fixed-length cell multiplexing/distributing system 501 usually comprises a fixed-length cell multiplexing/distributing processing unit 401 which is connected to a plurality of fixed-length cell transmitting/receiving devices 101-1 to 101-n (n is a natural number). The fixed-length cell multiplexing/distributing processing unit 401 is arranged so as to be able to collect monitor information from each of the fixed-length cell transmitting/receiving devices 101-i (i=1 to n).
The fixed-length cell multiplexing/distributing processing unit 401 comprises a fixed-length cell receiving section (TED LSI) 101, an overhead processing fixed-length cell receiving section (OH LSI) 102, a fixed-length cell multiplexing/distributing device (HUB LSI) 201, and a cell format preparation section (Ti TDC 1500A) 301. The fixed-length cell multiplexing/distributing device 201 comprises a fixed-length cell multiplexing section (Send) 201A and a fixed-length cell distributing section (Receive) 201B.
FIG. 40 is a block diagram which shows the configuration of the previously described general fixed-length cell multiplexing/distributing device 201. As shown in FIG. 40, the fixed-length cell multiplexing section 201A of the fixed-length cell multiplexing/distributing device 201 multiplexes fixed-length cells (sending-side processing), and the fixed-length cell distributing section 201B distributes the received fixed-length cells (receiving-side processing).
When the fixed-length cell multiplexing/distributing device 201 in the fixed-length cell multiplexing/distributing processing unit 401 receives information (fixed-length cells) from each fixed-length cell transmitting/receiving device 101-i other than the fixed-length fixed-length cell transmitting device 101-1, i.e., each of the cell transmitting/receiving devices 101-2 to 101-n, start-stop synchronous sections 202-2 to 202-n in the fixed-length cell multiplexing section 201A first carry out start-stop asynchronous processing for the input cells, and SPS (Start Parity Stop) bit detecting sections 203-1 to 203-n detect a start bit, a parity bit, a stop bit, etc.
The fixed-length cell transmitting device 101-1 handles the cells which should be sent in preference to the cells handled by the other fixed-length cell transmitting/receiving devices 101-2 to 101-n. As shown in FIG. 40, the information (OH) sent from the fixed-length cell transmitting device 101-1 is subjected to neither the start-stop synchronous processing performed by the start-stop synchronous sections 202-2 to 202-n nor detection of a start bit, a parity bit, and a stop bit carried out by the SPS bit detecting sections 203-2 to 203-n. The information is received by an acquiring section 206 in synchronous with a frame pulse of the fixed-length cell transmitting device 101-1. In this way, the cells handled by the fixed-length cell transmitting device 101-1 are sent in preference to any other cells.
The fixed-length cells are written into corresponding FIFO (First-in First-out) memory devices 204-2 to 204-n, respectively. At this time, for example, the fixed-length cell multiplexing section 201A monitors the FIFO memory devices 204-2 to 204-n, in that order, with respect to whether or not the cells have been written into the FIFO memory devices 204-2 to 204-n, as shown in FIG. 41. If the cells are written into the FIFO memory devices 204-2 to 204-n, the cells are read from the FIFO memory devices 204-1 to 204-n. The thus-read cells are respectively processed by time-division multiplexing in a multiplexing section 205, so that each cell is sent.
The fixed-length cell multiplexing/distributing system 501 gives priorities to the information items (i.e., fixedlength cells) which the fixed-length cell multiplexing/distributing processing unit 401 receives from the respective fixed-length cell transmitting/receiving devices 101-1 to 101-n. As a result, the proportion of the fixed-length cells lost due to receipt of excessive traffic is reduced, so that the cell loss ratio of the fixed-length cells which are sent preferentially (priority cells) is prevented from exceeding a predetermined level, thereby guaranteeing desired quality.
That is, even if the fixed-length cell to be processed is in excess of the maximum permissible amount, it becomes possible to send a priority cell by discarding such an amount of the information that the quality of the information is not significantly affected. As a result of this, the efficiency of multiplexing of the fixed-length cells can be improved.
On the other hand, when the fixed-length cell distributing section 201B receives a fixed-length cell, a write control section 43 detects, from the received fixed-length cell, the port number of a port to which the received cell is to be distributed. The received cell is then distributed to a corresponding one of the FIFO memory devices 204-1 to 204-n.
The thus-distributed cell is temporarily held in a corresponding one of the FIFO memory devices 204-1 to 204-n, and in a corresponding one of SPS bit adding sections 207-1 to 207-n, there is then added to the cell a start bit, a parity bit, and a stop bit . The resultant cell is then sent to the fixed-length cell transmitting/receiving device 101-i. The sending of a priority cell is not carried out in the above distributing operation.
FIG. 42 is a block diagram showing the internal configuration of the previously described fixed-length cell transmitting device 101-1. As shown in FIG. 42, the fixed-length cell transmitting device 101-1 comprises a fixed-length cell storage section (RAM) 150, a read counter 151, a JK flip-flop (JK-FF) circuit 153, an edge detecting section 154, and decoders 155-1 to 155-3.
The fixed-length cell storage section 150 stores input fixed-length cell data, and the read counter 151 reads the fixed-length cell data from the fixed-length cell storage section 150 in synchronism with internal frames each corresponding to a single fixed-length cell.
The JK flip-flop circuit 153 outputs a required signal on the basis of both a RAM write termination signal, which is output when the data have been written into the fixed-length cell storage section 150, and a signal output from a decoder 155-3 which will be described later. The edge-detecting section 154 detects the leading edge or trailing edge of the pulse signal output from the JK flip-flop circuit 153.
The decoder 155-1 generates a read enable signal for use in the fixed-length cell storage section 150, and the decoder 155-2 sends a frame pulse signal for use in the fixed-length cell multiplexing section 201A to the fixed-length cell multiplexing section 201A. The decoder 155-3 generates a RAM read termination signal which represents the completion of the reading of the fixed-length cell data.
When the fixed-length cell data are entered (i.e., written) into the fixed-length cell storage section 150 of the fixed-length cell transmitting device 101-1, the RAM write termination signal, for example, as shown in FIG. 43(g) is input to the JK flip-flop 153. As a result, the output of the JK flip-flop circuit 153 is switched to the high level, as shown in FIG. 43(h).
When the output of the edge detecting section 154 is switched to the high level, the read counter 151, which receives the output from the JK flip-flop circuit 153, starts a loading operation, so that the read counter 151 outputs its Q (data) output to the fixed-length cell storage section 150 as a read address (RADD) signal, as shown in FIG. 43(b). At this time, the read counter 151 further outputs a read enable (REN) signal as shown in FIG. 43(c) to the fixed-length cell storage section 150 via the decoder 155-1. A signal which is switched to the high level in synchronism with the read enable signal is output through the decoder 155-2 to the fixed-length cell multiplexing section 201A as a frame pulse for use in the fixed-length cell multiplexing section 201A, as shown in FIG. 43(e).
As previously described, when the fixed-length cell storage section 150 receives the read address signal and the read enable signal, a cell is read from the fixed-length cell storage section 150. When the reading of the cell has been completed, a RAM read termination signal as shown in FIG. 43(f) is output from the read counter 151 to the decoder 155-3. Arrows in FIG. 43 indicate timing clock signals.
FIG. 44 is a block diagram showing the configuration of the previously described fixed-length cell distributing section 201B. In brief, the fixed-length cell distributing section 201B is designed so as to carry out the processing in reverse to that of the multiplexing operation carried out by the fixed-length cell multiplexing section 201A. As shown in FIG. 44, the fixed-length cell distributing section 201B comprises a select (SEL) signal generating section 54A, a write control section 43, the FIFO memory (RAM) devices 204-1 to 204-n, read counters (RCTR) 45C-1 to 45C-n, and parallel/serial (P/S) converts 42-1 to 42-n.
The FIFO memory devices 204-1 to 204-n are disposed so as to correspond to respective output ports (DTOUT 1-n). Each of the FIFO memory devices 204-1 to 204-n stores a received fixed-length cell which in this case, comprises m parallel data strings (m is a natural number). The SEL signal generating section 54A detects the port number of a port to which the fixed-length cell is to be output, from the data of each fixed-length cell input as m-parallel data. The SEL signal generating section 54A then generates a signal (a port selecting signal) corresponding to the detected port number. For example, as shown in FIGS. 45(a) and 45(b), the number of the port to which the received cell is to be output is detected in synchronism with a received frame pulse (FP) signal (in the order of port numbers, that is, in this case, 1, 2, n, and 2). From the detected data is determined proper one of the FIFO memory devices 204-1 to 204-n into which the input cell is to be written, and the determined FIFO memory device is communicated to a write signal generating section 43A.
The write control section 43 writes the input data into the one of the FIFO memory devices 204-1 to 204-n corresponding to the port number that is detected by the SEL signal generating section 54A from the data of the fixed-length cell comprising M parallel data strings (hereinafter referred to as "M-parallel fixed-length cell"). The write control section 43 comprises a write enable signal (WEN) generating section 43A, a write counter (WCTR) 43B, and a read counter load (RCTRLD) signal generating section 43C.
The write signal generating section 43A generates a write enable (WEN) signal and a write counter load (WCRTRLD) signal for each of the FIFO memory devices 204-1 to 204-n corresponding to the respective ports, as shown in FIGS. 45(d) to 45(f). The write enable signal is output to the FIFO memory devices 204-1 to 204-n and the read counter load signal generating section 43C, whereas the write counter load signal is output to the write counter 43B.
The write counter 43B outputs its Q output, as a write address (WADD), to FIFO memory devices 204-1 to 204-n on the basis of information (i.e., a write counter load signal) received from the write signal generating section 43A. The write counter 43B notifies the read counter load signal generating section 43C that the information has been written into the FIFO memory devices 204-1 to 204-n (i.e., the write counter 43B sends a write termination signal to the read counter load signal generating section 43C). For example, when a write counter counts up as shown in FIG. 45(c), a write termination signal is output to the read counter load signal generating section 43C every time the writing of the cell data into the FIFO memory devices 204-1 to 204-n has been finished, as shown in FIGS. 45(g) to 45(i).
Upon receipt of the write enable signal from the write signal generating section 43A, the read counter load signal generating section 43C generates a read counter load signal on the basis of the write termination signal from the write counter 43B. This read counter load signal is input to read counters 45C-1 to 45C-n. The read counter load signal is produced for each of the ports.
In response to the read counter load signal from the read counter load signal generating section 43C, the read counters 45C-1 to 45C-n count up in the manner shown in, for example, FIGS. 45(j), 45(m), and 45(p). The read counters 45C-1 to 45C-n then generate read address (RADD) signals for use in the FIFO memory devices 204-1 to 204-n as well as read enable (REN) signals as shown in FIGS. 45(k), 45(n), and 45(q). The fixed-length cell data are sequentially read from the FIFO memory devices 204-1 to 204-n on the basis of the read enable signals (see FIGS. 45(l), 45(o), and 45(r)). The thus-read fixed-length cell data are sent to P/S converting sections 42-1 to 42-n.
In the multiplexing operation of this type of general fixed-length cell multiplexing/distributing device 201, the FIFO memory devices 204-1 to 204-n corresponding to the ports are monitored, in that order, from the FIFO memory device 204-1 in response to respective monitor enable signals, as shown in FIGS. 46(a) to 46(c). Therefore, if, as shown in FIG. 46(d), the FIFO memory device 204-1 is monitored in accordance with the monitor enable signal (indicated by 1 in FIG. 46) before the writing of the fixed-length cell data into the FIFO memory device 204-1 has been completed, the fixed-length cell data are judged as being unfixed. As a result, the fixed-length cell data are not read.
On the other hand, if, as shown in FIG. 46(e), the FIFO memory device 204-n is monitored in accordance with a corresponding monitor enable signal (indicated by 2 in FIG. 46) after the writing of the fixed-length cell data into the FIFO memory device 204-n has been completed, the fixed-length cell data of the FIFO memory device 204-n are judged as being fixed. As a result, that fixed-length cell data are read.
The previously described fixed-length cell data, which are received by the FIFO memory device 204-1 and are determined as being unfixed, are read by the next monitor enable signal (indicated by 3 in FIG. 46). Consequently, the data stored in the FIFO memory device 204-1 which stores the highest-priority fixed-length cell data cannot be sent preferentially, and the fixed-length cell data following the highest-priority fixed-length cell data are sent most preferentially, as shown in FIG. 46(f).
The higher the number of virtual channels to be processed, the poorer the authenticity of first-come, first-served processing. If, in the course of the processing carried out in the fixed-length cell multiplexing section 201A and subsequent sections, the amount of the fixed-length cell data exceeds the storage amount of the FIFO memory devices 204-1 to 204-n, the highest-priority fixed-length cell data may be abandoned due to congestion, which in turn results in an increase in the length of delay. In the preferential processing for simultaneously arrived fixed-length cells, it is substantially impossible to accurately specify the port whose fixed-length cell is to be preferentially output, because of the difference in the order of monitor positions.
With regard to the distribution processing, each port is provided with the corresponding one of the FIFO memory devices 204-1 to 204-n, and read control sections (i.e., the read counters) are provided so as to correspond to the number of the memory devices, which resulting in an increase in a circuit scale. Further, the subsequent fixed-length cell data are immediately output after certain fixed-length cell data have been output, which makes it difficult to distinguish these two fixed-length cells from each other and, eventually, this results in inferior processing capability.